In a wiring substrate such as, for example, a package substrate and a system board, a signal reflection may be suppressed to improve the signal quality by keeping the ratio of the inductance and capacitance constant (i.e., by performing an impedance matching) in a path through which the electrical signal passes. As a result, an impedance matching technology has been developed in which an impedance matching is performed in wirings or vias within a substrate. For example, a design method has been developed in wiring micro-strip lines, in which a conductor distance between signal-ground or the width of a signal wiring is adjusted according to the permittivity of an insulation material such that the impedance approaches a desired value.
When a portion of the signal path has different characteristic impedance, a signal reflection occurs at the boundary surface of the portion where the characteristic impedance is different. When a high frequency signal is applied, it has become a recent problem that a signal reflection occurs in a bonding portion between wiring substrates due to the change of the ratio of the inductance and capacitance.
For example, as illustrated in FIG. 19, when a semiconductor package 61 is mounted on a system board 71, an electrode pad 62 of the semiconductor package 61 and an electrode pad 72 of the system board 71 are bonded each other with a solder ball 81. Since the electrode pad 62 of the semiconductor package 61 is far bigger than a conductor pattern (wirings and vias) 63 of the semiconductor package 61, an impedance mismatch occurs to increase the signal reflection when the high frequency signal is used. As illustrated in FIG. 20, since the solder ball 81 is large even if the size of the electrode pad 62 of the semiconductor package 61 becomes small, an impedance mismatch occurs increasing the signal reflection at the high frequency range as in the case where the electrode pad 62 of the semiconductor package 61 is large.
When the impedance matching is performed by reducing the size of the electrode pad 62 of the semiconductor package 61 and the solder ball 81, the height of the solder ball 81 is lowered by making the solder ball 81 small. When the height of the solder ball 81 is lowered, the solder ball 81 may not be bonded to the semiconductor package 61 or the system board 71 due to the deformation such as, for example, the flexure or wrinkling of the semiconductor package 61 and the system board 71, as illustrated in FIG. 21. The semiconductor package 61 and the system board 71 suffer from an expansion and a shrinkage caused by the temperature change. As a result, in order to maintain the bonding between the semiconductor package 61 and the system board 71, it is not advisable to reduce the size of the solder ball 81.
The following is reference documents:    [Document 1] Japanese Laid-Open Patent Publication No. H08-236655,    [Document 2] Japanese Laid-Open Patent Publication No. 2002-299502,    [Document 3] Japanese Laid-Open Patent Publication No. 2006-339563,    [Document 4] Japanese Laid-Open Patent Publication No. 2009-55019,    [Document 5] Japanese Laid-Open Patent Publication No. 2010-219463,    [Document 6] Japanese Laid-Open Patent Publication No. H08-78797,    [Document 7] Japanese National Publication of International Patent Application No. 2002-543603,    [Document 8] Japanese Laid-Open Patent Publication No. H07-273146, and    [Document 9] Japanese Laid-Open Patent Publication No. 2000-223819.